Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of charge storage nodes such as floating gates or trapping layers or other physical phenomena, determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
Two common types of flash memory array architectures are the “NOR” and “NAND” architectures. These architectures are named for the resemblance that the basic memory cell configuration of each architecture has to a basic NOR or NAND gate circuit, respectively.
In the conventional NOR array architecture, floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by select lines, conventionally referred to as “word lines”, and their drains are connected to transfer lines that are conventionally referred to as bit or digit lines. Memory cells having their control gates connected to a common select line are considered to be a “row” of memory cells while memory cells having their drains connected to a common transfer line are considered to be a “column” of memory cells. The source of each floating gate memory cell is typically connected to a common source line. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word line connected to their control gates. The row of selected memory cells then place their stored data values on the bit lines by flowing a differing current if in a programmed state or not programmed state from the connected source line to the connected bit line.
A NAND architecture arranges its array of non-volatile memory cells in a matrix of rows and columns so that the gates of each non-volatile memory cell of the array are coupled by rows to word lines. However, unlike NOR, each memory cell is not directly coupled to a source line and a bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are coupled together in series, source to drain, between a common source line and a column bit line. It is noted that other non-volatile memory array architectures exist, including, but not limited to AND arrays, OR arrays, and virtual ground arrays.
One problem with programming in a NAND memory array is program disturb. Program disturb refers to the increase of the threshold voltages of memory cells in a bit line and/or a word line containing a memory cell being programmed. The threshold voltage increase is a result of the programming voltage that is applied to the cell being programmed affecting other cells coupled to the bit line/word line as well. Program disturb can result in an unprogrammed cell being programmed or a programmed cell changing states.
One method used to reduce program disturb is a boosting scheme that biases unselected word lines with a program inhibit voltage. For example, the unselected word lines in a NAND series string of memory cells can be biased with 10V. The unselected word lines couple to unselected bit lines causing a voltage to exist in the channel of the unselected bit lines. This tends to reduce the disturb condition.
A problem with this scheme is that punch-through can occur on nearby word lines in the same series string if these cells are turned off. The effect of punch-through is to increase the threshold voltage for the cells coupled to the affected word lines. Typically punch-through has the greatest affect on the source-side word lines of the selected word line.
For the reasons stated above, and for other reasons which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing a punch-through disturb effect in a memory device.